As integrated circuits have continued to increase in complexity and integration density, it has become a common practice to arrange the conducting, metallization layers in multiple, vertically spaced layers insulated from one another by a dielectric layer. However, when multiple layers of dielectric and conductive material are formed, difficulties may arise, particularly in the formation of the upper metallization levels, as a result of the uneven topography of the underlying dielectric layers. When a dielectric layer is deposited over a metal conducting layer, for example, the surface of the dielectric layer exhibits peaks at the locations of the metal layers, and valleys or depressions at the open areas at which no metal layers are formed. This unevenness in the levels of the dielectric layer becomes more pronounced as the number of metallization layers increases. To minimize the effects of these irregularities in the levels of the dielectric layers and to improve lithography and metal step coverage, it is necessary to improve the planarization of the dielectric layers.
One technique that has been used to achieve greater planarization of the intervening dielectric layers is chemical mechanical polishing (CMP), which technique is often used in high-volume manufacturing in place of conventional planarization techniques, such as resist etchback. Planarization is achieved in a CMP process by polishing the dielectric surface on a rotating abrasive pad, while a slurry is applied to help lubricate and break down the bonds of the underlying surface. As the surface is polished, the peaks on the dielectric layer are polished before the valleys, resulting in a more even dielectric layer. After planarization of the dielectric layer is completed, a conductive layer is applied over the planarized dielectric layer, which is then photolithographically patterned and etched to define signal lines and conductive layer interconnects. Whereas CMP has been found to be an effective way to achieve improved planarization in a multi-level metallization integrated circuit, it is a relatively expensive process.
Another approach that has been used to achieve improved planarization in a multi-level metallization process is to deposit otherwise unused dummy lines or dummy features in the open areas between the locations of the metal lines so that subsequent dielectric deposition will not exhibit the valleys at the open areas. This has been achieved in the past by searching the entire chip layout to locate the open areas for each metallization layer, and then preparing a mask that is specific to the open area locations for that particular layer. That mask is thereafter employed along with conventional photolithographic steps to selectively form dummy lines in the open areas between metallization lines for each metallization layer. However, since each chip has a different pattern of metal lines and open areas, a unique mask must be fabricated to produce the dummy lines for each different layout based on a search of the chip for open areas. This process is relatively time consuming and costly.
It is thus an object of the present invention to provide a method for fabricating a multilevel integrated circuit that adds minimal complexity to the fabrication process and which is independent of the particular metallization line and open area patterns of the chip.
It is a further object of the invention to provide a method for fabricating metallization layers in a multi-level integrated circuit which can be implemented at the computer-aided-design (CAD) stage rather than during the processing level.
It is an additional object of the present invention to provide a method of the type described in which dummy features are implemented in open areas without the need to search the entire chip layout for open areas.